Manufacturing of semiconductor devices involves many patterning steps. Each of these patterning steps or patterning processes may in turn include several sub-steps or sub-processes. A typical patterning process may include, for example, creation of a photomask, use of the photomask in an optical exposure tool to expose a photosensitive material (“photoresist”) applied on a wafer, development and rinse of the photoresist, and one or more etching steps to transfer patterns created in, and from, the photoresist to an underlying film or semiconductor substrate.
As is known in the art, some of these processes or sub-processes may have inherent nonlinearities and/or imperfections that need to be corrected. Such corrections may be accomplished by pre-distorting designs of patterns that are created in the photomask, through applying an industry standard methodology commonly known as Optical Proximity Correction (OPC), wherein one or more of the sub-processes are first characterized and/or modeled inside an OPC model or simulation package, and then the design of patterns for the semiconductor device is modified to account for the nonlinearity impact.
Accurately modeling of patterning processes is a critical and must-go-through step in any development of new semiconductor process technologies. So far, calibration of models used inside an OPC model or simulation package has proven to be a time consuming and resource intensive task. It is anticipated that reduction in this calibration cycle time shall lead to faster technology development and improve time-to-market deployment of next generation processes. On the other hand, long calibration cycle time may reduce the ability to quickly improve processes and/or incorporate improvements in unit process area into process-of-record (POR). For example, if a mask maker makes improvement in their mask making process and is ready to implement that process, they may need to wait until the next “OPC cycle” when models used inside OPC are updated and new photomasks are ordered. In other words, activities of the mask maker may need to be synchronized with the OPC cycle. Such OPC cycle could lead to, for example, a 6-month delay in the introduction of a newly improved process.
The reason that all unit processes are required to be synchronized with the so-called “OPC cycles” is due to the coupling of various processes used inside the OPC model. For instance, mask effects are generally not accounted for during OPC model build, and those mask effects typically get coupled with photoresist effects in the “resist model.” Likewise, some optical effects may also be coupled into the resist model. The result of these coupling is that any changes to the mask, the optical, and/or the photoresist processes will require a complete rebuild of the resist model and possibly the optical model as well. This coupling effect and synchronizing of unit processes may ultimately cause longer time for the OPC cycle because, for each model rebuild, all the components inside the model must be rebuilt.
FIG. 1 is a flowchart illustration of a method, as is known in the art, for calibrating a lumped-process-model using measured wafer data. The process typically starts with the design of test patterns (101). The test patterns are generally designed and/or selected such that they are able to cover the parameter space of interested images adequately. These test patterns are then made into OPC patterns (102) with the latest OPC keywords and assembled subsequently into a test mask design (103). Using test mask design 103, masks with test patterns (105) are then built or fabricated (104) using the latest mask manufacturing process.
Next, send-ahead-wafers are processed and a set of center process conditions (106) is determined. Wafers, or semiconductor wafers, for calibration are then processed (107) under the determined center process conditions and, possibly, other process conditions at variations to the center process conditions. The result is one or more fabricated semiconductor wafers (108) onto which images of test patterns (101) are transferred. The test patterns 101 printed on the wafers may capture, and/or bear characteristics of, the nonlinearities of the patterning process.
In the meantime, SEM-to-physical offsets may be pre-determined (109) for the patterning process and these offset values are used to help determine the center process conditions (106) and in measuring the calibration patterns. Subsequently, new SEM (scanning-electron-microscope) recipes are built based upon the latest test mask design and the results measured from fabricated wafers (110). The SEM data set may go through a filtering process (111) to remove bad measurement data. Finally, the filtered SET data set may be applied in the calibration (112) of a lumped-process-model (113).
In order to reduce cycle time of the above process, attempts have been made to skip some of the individual steps whenever possible. For example, if the SEM-to-physical offset values are already known for a given process and/or a given SEM tool, then that step (109) may be skipped. However, skipping a couple of individual steps will rarely reduce more than a few weeks off of the overall cycle time, which may span over, for example, a 6-month time period depending on various factors. Meanwhile, many of the more time consuming steps such as, for example, processing the wafers (107) and collecting data by measuring the processed wafers (110), may not be skipped and may not be performed in parallel.
FIG. 2 is a flowchart illustration of a wafer image simulation flow, as is known in the art, using a lumped-process-model. As is known in the art, after the lumped process model (113) is properly calibrated as being illustrated in FIG. 1, shapes (201) designed for a particular semiconductor device or device interconnect may be directly simulated using the calibrated lumped-process-model (202) to give prediction of expected wafer images (203), which may be pre-distorted wafer image as described above. Theoretically, to the extent that the lumped-process-model accurately represents the process, the wafer images may include all of the nonlinearities of the patterning process that is being modeled.
Still, lumped-process-models using the above process modeling lacks proper predictive accuracy. For example, when using an OPC model to predict the behavior or characteristics of a process under certain expected process variations and/or nominal changes in process conditions, the model may suffer from having too many processes being coupled together in an empirical “resist model”. On the other hand, if each process was to be modeled independently with physically based models, variations in those processes may be properly accounted for. However, in order to do so, physical model forms and improved calibration methodologies are needed but these physical models are generally too slow to provide useful simulations on real semiconductor layouts.
In order to improve predictive accuracy of the lumped-process-model, attempts were also made to separate out one or more sub-processes that may be modeled physically and have the lumped-process-model describing only the non-physically-modeled effects. For example, in photolithography, a large portion of the overall patterning nonlinearity comes from the optical exposure step and this step may be modeled in relative accuracy with physical models. In this situation, it may be more appropriate to simulate the optical exposure step in physical models, and capture only the photo-mask and photo-resist related nonlinearities in a single lumped-process-model. The method used to calibrate such a hybrid model is illustrated in FIG. 1 at step 114. Specifically, physical models (114) may be used to simulate the test patterns associated with the optical exposure, the results of which may then be provided in the following calibration step (112) to calibrate the lumped-process-model (113). In this modified approach, the lumped-process-model 113 approximately represents the nonlinearities of all of the non-physically-modeled sub-processes. However, this approach still couples several effects together in a non-physical manner which does not allow a sub-process to be replaced with a new process without the significant loss of accuracy. In order to maintain good accuracy, a complete recalibration of the lumped-process-model is required whenever one of the sub-processes, including those that have physical models, is changed.
When utilizing the above hybrid, physical/lumped-process-model approach, simulation flow may be modified accordingly as being illustrated in FIG. 2. For example, test patterns (201) may be first simulated with the physical models (204). Results from the physical models (204) may then be fed as input to the simulation using the lumped process model (202) to create wafer image (203).
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity.